From 2f56305e5ca7a99d1cbe34a8d72f69ecc78fd19c Mon Sep 17 00:00:00 2001 From: Andrzej Kaczmarek Date: Wed, 27 Sep 2017 13:08:29 +0200 Subject: [PATCH] nimble/phy: Allow extra t_ifs margin on receive This is only for debugging purposes as some controllers violate t_ifs and we won't be now able to maintain connection with such hw. X-Original-Commit: a0434c3fd666ea049318b866ca625ab483c34716 --- nimble/drivers/nrf52/src/ble_phy.c | 11 +++++++++++ nimble/drivers/nrf52/syscfg.yml | 10 ++++++++++ 2 files changed, 21 insertions(+) diff --git a/nimble/drivers/nrf52/src/ble_phy.c b/nimble/drivers/nrf52/src/ble_phy.c index d8662fb14..976645322 100644 --- a/nimble/drivers/nrf52/src/ble_phy.c +++ b/nimble/drivers/nrf52/src/ble_phy.c @@ -484,6 +484,17 @@ ble_phy_wfr_enable(int txrx, uint8_t tx_phy_mode, uint32_t wfr_usecs) end_time += g_ble_phy_t_txenddelay[tx_phy_mode]; /* Wait a bit longer due to allowed active clock accuracy */ end_time += 2; +#if MYNEWT_VAL(BLE_PHY_CODED_RX_IFS_EXTRA_MARGIN) > 0 + if ((phy == BLE_PHY_MODE_CODED_125KBPS) || + (phy == BLE_PHY_MODE_CODED_500KBPS)) { + /* + * Some controllers exceed T_IFS when transmitting on coded phy + * so let's wait a bit longer to be able to talk to them if this + * workaround is enabled. + */ + end_time += MYNEWT_VAL(BLE_PHY_CODED_RX_IFS_EXTRA_MARGIN); + } +#endif } else { /* * RX shall start no later than wfr_usecs after RX enabled. diff --git a/nimble/drivers/nrf52/syscfg.yml b/nimble/drivers/nrf52/syscfg.yml index 6eba0ed09..b4088aa10 100644 --- a/nimble/drivers/nrf52/syscfg.yml +++ b/nimble/drivers/nrf52/syscfg.yml @@ -19,6 +19,16 @@ # Package: hw/drivers/nimble/nrf52 syscfg.defs: + BLE_PHY_CODED_RX_IFS_EXTRA_MARGIN: + description: > + This defines additional margin for T_IFS tolerance while in + RX on coded phy to allow maintaining connections with some + controllers that exceed proper T_IFS (150 usecs) by more + than allowed 2 usecs. + This value shall be only used for debugging purposes. It is + strongly recommended to keep this settings at default value + to ensure compliance with specification. + value: 0 BLE_PHY_DBG_TIME_TXRXEN_READY_PIN: description: > When set to proper GPIO pin number, this pin will be set